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Tickless Mode

One common necessity is to create system designed to work in very low power environments. The traditional RTOS approach can be problematic because the continuous system tick interrupt prevents the system to use deep sleep modes, the CPU is continuously woken by mostly unnecessary interrupts.

A Different Approach

The system tick is usually used to perform two tasks:

  1. Increase a system time variable.
  2. Handle timeouts in the RTOS API.

In ChibiOS/RT and ChibiOS/NIL the two above tasks are handled in a peculiar way:

System Time Handling

The HW counter of a physical timer is used as system time, the counter is incremented regardless of the RTOS state and does not generate interrupts. This makes a periodic interrupt not necessary.

Timeouts Handling

Instead of implementing software timers using a periodic tick, RT and NIL schedule in advance the time of the next interrupt. This means that an interrupt will be generated only if required and only at the appropriate time.

Note that this is true at all time, the system does not just suppress ticks while idling but also while executing tasks.

Idle Hooks

Thanks to the tickless mode the CPU can stay in a sleep state for much longer, in a typical application, seconds instead of milliseconds.

In order to take advantage of this both RT and NIL offer two hook macros that are executed when:

  1. The system is entering the idle task.
  2. The system is leaving the idle task.

The hooks can be used to enter/leave low power modes, scale down clocks, stop specific peripherals and so on. You don't need to force the system doing what you need, everything is there for you to implement your desired low power management.


The tickless mode is activated by default because its advantages are overwhelming:

  • Power management is much easier to implement.
  • The system time can have a much higher resolution because there is no worry about continuous IRQ flooding caused by the system tick.
  • The system is more efficient on average because there is no time lost in serving unneeded IRQs, less code executed means less power and better response time.


The tickless mode requires a more complex software implementation so the kernel grows larger of about 256 bytes. It also require a dedicated HW timer with the following features:

  • 16 or 32 bits up-counting counter register. 32 bits is recommended.
  • A comparator register able to generate an interrupt when the counter register matches its value.

Unfortunately the Cortex-M SysTick timer does not met the above requirements so a platform timer must be used. The classic tick mode is also available in case that power is not a concern or a compatible timer is not available.

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